HD6417751 Datasheet, PDF (343/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 12.3 TMU Interrupt Sources
Channel
0
1
2
3
4
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
TUNI3
TUNI4
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
Underflow interrupt 3
Underflow interrupt 4
12.5 Usage Notes
12.5.1 Register Writes
When performing a TMU register write, timer count operation must be stopped by clearing the
start bit (STR0–STR4) for the relevant channel in the timer start register (TSTR, TSTR2).
Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF)
and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared
while the count is in progress. When the flags (UNF and ICPF) are cleared while the count is in
progress, make sure not to change the values of bits other than those being cleared.
12.5.2 TCNT Register Reads
When performing a TCNT register read, processing for synchronization with the timer count
operation is performed. If a timer count operation and register read processing are performed
simultaneously, the TCNT counter value prior to the count-down operation is read by means of the
synchronization processing.
12.5.3 Resetting the RTC Frequency Divider
When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider
should be reset.
12.5.4 External Clock Frequency
Ensure that the external clock frequency for any channel does not exceed Pφ/4.
Rev. 3.0, 04/02, page 303 of 1064