HD6417751 Datasheet, PDF (153/1105 Pages) Renesas Technology Corp – SuperH RISC engine

4.7 Store Queues
Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory.
When not using the SQs, the low power dissipation power-down modes, in which SQ functions
are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be
accessed while SQ functions are stopped. See section 9, Power-Down Modes, for the procedure
for stopping SQ functions.
4.7.1 SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store
queues can be set independently.
SQ0 ^{SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7]}
SQ1 ^{SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7]}
4B
4B
4B
4B
4B
4B
4B
4B
Figure 4.16 Store Queue Configuration
4.7.2 SQ Writes
A write to the SQs can be performed using a store instruction on P4 area H'E000 0000 to H'E3FF
FFFC. A longword or quadword access size can be used. The meaning of the address bits is as
follows:
[31:26]:
[25:6]:
[5]:
[4:2]:
[1:0]
111000
Don’t care
0/1
LW specification
00
Store queue specification
Used for external memory transfer/access right
0: SQ0 specification 1: SQ1 specification
Specifies longword position in SQ0/SQ1
Fixed at 0
4.7.3 Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).
Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from
the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is
always at a 32-byte boundary. While the contents of one SQ are being transferred to external
memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in
the transfer to external memory is deferred until the transfer is completed.
Rev. 3.0, 04/02, page 113 of 1064