HD6417751 Datasheet, PDF (732/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)
Pφ (MHz)
N
7.1424 10.00
10.7136 14.2848 25.0
0
9600.0 13440.9 14400.0 19200.0 33602.2
1
4800.0 6720.4 7200.0 9600.0 16801.1
2
3200.0 4480.3 4800.0 6400.0 11200.7
Note: Bit rates are rounded to one decimal place.
33.0
44354.8
22177.4
14784.9
50.0
67204.3
33602.2
22401.4
The method of calculating the value to be set in the bit rate register (SCBRR1) from the peripheral
module operating frequency and bit rate is shown below. Here, N is an integer in the range 0 ≤ N ≤
255, and the smaller error is specified.
N
=
1488
Pφ
× 2^2n–1
×
B
×
10⁶
–
1
Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0)
Bits/s
9600
7.1424
N Error
0 0.00
10.00
N Error
1 30.00
10.7136
N Error
1 25.00
Pφ (MHz)
14.2848
N Error
1 8.99
25.00
N Error
3 14.27
33.00
N Error
4 8.22
50.00
N Error
6 0.01
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
Pφ (MHz)
Maximum Bit Rate (bits/s)
N
n
7.1424
19200
0
0
10.00
26882
0
0
10.7136
28800
0
0
16.00
43010
0
0
20.00
53763
0
0
25.0
67204
0
0
30.0
80645
0
0
33.0
88710
0
0
50.0
67204
0
0
Rev. 3.0, 04/02, page 692 of 1064