HD6417751 Datasheet, PDF (538/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bus returned to CPU
Bus cycle
CPU
CPU
CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
CPU
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers
data continuously until the transfer end condition is satisfied. Bus release by means of %5(4 and
refresh requests conform to the DMAC burst mode transfer priority specification in bus control
register 1 (BCRL.DMABST). With '5(4 low level detection in external request mode, however,
when '5(4 is driven high the bus passes to another bus master after the end of the DMAC
transfer request that has already been accepted, even if the transfer end condition has not been
satisfied.
Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in
this example are single address mode and '5(4 level detection (CHCRn.DS = 0, CHCRn.TM =
1).
Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 14.10 Example of DMA Transfer in Burst Mode
Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode
setting can also be made.
Rev. 3.0, 04/02, page 498 of 1064