HD6417751 Datasheet, PDF (407/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Area 2: For area 2, external address bits A28 to A26 are 010.
SRAM, MPX, and synchronous DRAM can be set to this area.
When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A2SZ1 and
A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected
with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM interface is set,
select 32 bit with the SZ bits in the MCR register. For details, see Memory Bus Width in section
13.1.5.
When area 2 is accessed, the &6 signal is asserted.
When SRAM interface is set, the 5' signal, which can be used as 2(, and write control signals
:( to :(, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A2W2 to A2W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (5'<).
The read/write strobe signal address and &6 setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3
register.
When synchronous DRAM interface is set, the 5$6 and &$6 signals, RD/:5 signal, and byte
control signals DQM0 to DQM3 are asserted, and address multiplexing is performed. 5$6, &$6,
and data timing control, and address multiplexing control, can be set using the MCR register.
Area 3: For area 3, external address bits A28 to A26 are 011.
SRAM, MPX, DRAM, and synchronous DRAM, can be set to this area.
When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A3SZ1 and
A3SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected
with bits A3SZ1 and A3SZ0 in the BCR2 register. When DRAM interface is set, 16 or 32 bits can
be selected with the SZ bits in the MCR register. When synchronous DRAM interface is set, select
32 bit with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5.
When area 3 is accessed, the &6 signal is asserted.
When SRAM interface is set, the 5' signal, which can be used as 2(, and write control signals
:( to :(, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (5'<).
Rev. 3.0, 04/02, page 367 of 1064