HD6417751 Datasheet, PDF (332/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or
stopped.
Bit 1: STR1
0
1
Description
TCNT1 count operation is stopped
TCNT1 performs count operation
(Initial value)
Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or
stopped.
Bit 0: STR0
0
1
Description
TCNT0 count operation is stopped
TCNT0 performs count operation
(Initial value)
12.2.3 Timer Start Register 2 (TSTR2)
TSTR2 is an 8-bit readable/writable register that specifies whether the channel 3 and 4 timer
counters (TCNT) are operated or stopped.
TSTR2 is initialized to H'00 by a power-on reset. TSTR retain their contents in standby mode.
When standby mode is entered when the value of either STR3 or STR4 is 1, the count halts when
the peripheral module clock stops and restarts when the clock supply is resumed.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
STR4 STR3
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W
R/W
Bits 7 to 2—Reserved: These bits are always read as 0. A write to these bits is invalid, but the
write value should always be 0.
Bit 1—Counter Start 4 (STR4): Specifies whether timer counter 4 (TCNT4) is operated or
stopped.
Bit 1: STR4
0
1
Description
TCNT4 count operation is stopped
TCNT4 performs count operation
(Initial value)
Rev. 3.0, 04/02, page 292 of 1064