HD6417751 Datasheet, PDF (729/1105 Pages) Renesas Technology Corp – SuperH RISC engine

If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)
to request retransmission of the data. After outputting the error signal for the prescribed length
of time, the receiving station places the signal line in the high-impedance state again. The
signal line is pulled high again by a pull-up resistor.
5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data
frame.
If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data.
17.3.4 Register Settings
Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or
1 must be set to the value shown. The setting of other bits is described below.
Table 17.3 Smart Card Interface Register Settings
Register Bit 7 Bit 6 Bit 5
SCSMR1 GM
0
1
SCBRR1 BRR7 BRR6 BRR5
SCSCR1 TIE
RIE
TE
SCTDR1 TDR7 TDR6 TDR5
SCSSR1 TDRE RDRF ORER
SCRDR1 RDR7 RDR6 RDR5
SCSCMR1 —
—
—
SCSPTR1 EIO
—
—
Note: A dash indicates an unused bit.
Bit
Bit 4 Bit 3
O/
1
BRR4 BRR3
RE
0
TDR4 TDR3
FER/ERS PER
RDR4 RDR3
—
SDIR
—
SPB1IO
Bit 2 Bit 1
0
CKS1
BRR2 BRR1
0
CKE1
TDR2 TDR1
TEND 0
RDR2 RDR1
SINV —
SPB1DT SPB0IO
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
SPB0DT
Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag
setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to
select the clock output state.
The O/ bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the
inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section
17.3.5, Clock.
Rev. 3.0, 04/02, page 689 of 1064