HD6417751 Datasheet, PDF (375/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 31 to 29—Area 6 Wait Control (A6W2–A6W0): These bits specify the number of wait
states to be inserted for area 6. For the case where an MPX interface setting is made, see table
13.7.
Bit 31: A6W2
0
1
Bit 30: A6W1
0
1
0
1
Bit 29: A6W0
0
1
0
1
0
1
0
1
Description
First Cycle
Inserted Wait States 5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
6
Enabled
9
Enabled
12
Enabled
15 (Initial value)
Enabled
Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to
be inserted from the second data access onward at the time of setting the burst ROM in a burst
transfer.
Bit 28: A6B2
0
1
Bit 27: A6B1
0
1
0
1
Bit 26: A6B0
0
1
0
1
0
1
0
1
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted
from Second Data
Access Onward
5'< Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
4
Enabled
5
Enabled
6
Enabled
7 (Initial value)
Enabled
Rev. 3.0, 04/02, page 335 of 1064