HD6417751 Datasheet, PDF (689/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred
from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or
greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control
register (SCFCR2).
Bit 1: RDF
0
Description
The number of receive data bytes in SCFRDR2 is less than the receive
trigger set number
(Initial value)
[Clearing conditions]
• Power-on reset or manual reset
• When SCFRDR2 is read until the number of receive data bytes in
SCFRDR2 falls below the receive trigger set number after reading RDF
= 1, and 0 is written to RDF
• When SCFRDR2 is read by the DMAC until the number of receive data
bytes in SCFRDR2 falls below the receive trigger set number
1
The number of receive data bytes in SCFRDR2 is equal to or greater than
the receive trigger set number
[Setting condition]
When SCFRDR2 contains at least the receive trigger set number of receive
data bytes*
Note: * SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set
number of data bytes can be read. If all the data in SCFRDR2 is read and another read is
performed, the data value will be undefined. The number of receive data bytes in SCFRDR2
is indicated by the lower bits of SCFDR2.
Rev. 3.0, 04/02, page 649 of 1064