HD6417751 Datasheet, PDF (561/1105 Pages) Renesas Technology Corp – SuperH RISC engine

1. Normal data transfer mode (channel 0)
%$9/ (the data bus available signal) is asserted in response to '%5(4 (the data bus request
signal) from an external device. Two CKIO-synchronous cycles after %$9/ is asserted, the
external data bus drives the data transfer setting command (DTR command) in synchronization
with 75 (the transfer request signal). The initial settings are then made in the DMAC channel
0 control register, and the DMA transfer is processed.
2. Normal data transfer mode (except channel 1 to channel 3)
In this mode, the data transfer settings are made in the DMAC from the CPU, and DMA
transfer requests only are performed from the external device.
As in 1 above, '%5(4 is asserted from the external device and the external bus is secured,
then the DTR command is driven.
The transfer request channel can be specified by means of the two ID bits in the DTR
command.
3. Handshake protocol using the data bus (valid for channel 0 only)
This mode is only valid for channel 0.
After the initial settings have been made in the DMAC channel 0 control register, the DDT
module asserts a data transfer request for the DMAC by setting the DTR command ID = 00,
MD = 00, and SZ ≠ 101, 110 and driving the DTR command.
4. Handshake protocol without use of the data bus
The DDT module includes a function for recording the previously asserted request channel. By
using this function, it is possible to assert a transfer request for the channel for which a request
was asserted immediately before, by asserting 75 only from an external device after a transfer
request has once been made to the channel for which an initial setting has been made in the
DMAC control register (DTR command and data transfer setting by the CPU in the DMAC).
5. Direct data transfer mode (valid for channel 2 only)
A data transfer request can be asserted for channel 2 by asserting '%5(4 and 75
simultaneously from an external device after the initial settings have been made in the DMAC
channel 2 control register.
Rev. 3.0, 04/02, page 521 of 1064