HD6417751 Datasheet, PDF (1081/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Appendix C Mode Pin Settings
The MD10–MD0 pin values are input in the event of a power-on reset via the #$% pin.
Clock Modes
Table C.1 Clock Operating Modes (SH7751)
Clock
Operating
Mode
0
1
2
3
4
5
External
Pin Combination
MD2 MD1 MD0
0
0
0
1
1
0
1
1
0
0
1
1/2
Frequency
Divider
Off
Off
On
Off
On
Off
Frequency
(vs. Input Clock)
Peripheral
CPU Bus Module
PLL1 PLL2 Clock Clock Clock
On On 6
3/2 3/2
On On 6
1
1
On On 3
1
1/2
On On 6
2
1
On On 3
3/2 3/4
On On 6
3
3/2
FRQCR
Initial Value
H'0E1A
H'0E23
H'0E13
H'0E13
H'0E0A
H'0E0A
Table C.2 Clock Operating Modes (SH7751R)
Clock
Operating
Mode
External
Pin Combination
MD2 MD1 MD0
PLL1
CPU
PLL2 Clock
Frequency
(vs. Input Clock)
Bus Peripheral
Clock Module Clock
FRQCR
Initial Value
0
0
0
0
On (×12) On 12
3
3
H'0E1A
1
1
On (×12) On 12
3/2
3/2
H'0E2C
2
1
0
On (×6) On 6
2
1
H'0E13
3
1
On (×12) On 12
4
2
H'0E13
4
1
0
0
On (×6) On 6
3
3/2
H'0E0A
5
1
On (×12) On 12
6
3
H'0E0A
6
1
0
OFF (×6) OFF 1
1/2
1/2
H'0808
Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode.
2. For the ranges input clock frequency, see the description of the EXTAL clock input
frequency (f_EX) and the CKIO clock output (f_OP) in section 23.3.1, Clock and Control
Signal Timing.
Rev. 3.0, 04/02, page 1041 of 1064