HD6417751 Datasheet, PDF (415/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D31–D0
(read)
D31–D0
(write)
T1
Tw
T2
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.10 SRAM Interface Wait Timing (Software Wait Only)
Rev. 3.0, 04/02, page 375 of 1064