HD6417751 Datasheet, PDF (856/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 6: PER
0
1
Description
Ignore detected parity errors
Respond to detected parity error
(Initial value)
Bit 5—VGA Pallet Snoop Control (VPS)
Bit 5: VPS
0
1
Description
VGA-compatible device
(Initial value)
The device does not respond to pallet register writes (not supported)
Bit 4—Memory Write and Invalidate Control (MWIE): Controls the issuance of memory and
invalidate command when the PCIC is operating as the master.
Bit 4: MWIE
0
1
Description
The device uses memory write
(Initial value)
The device can execute memory write and invalidate commands (not
supported)
Bit 3—Special Cycle Control (SPC): Shows whether special cycles are supported when the
PCIC is operating as a target.
Bit 3: SPC
0
1
Description
Ignore special cycle
Monitor special cycle (not supported)
(Initial value)
Bit 2—PCI Bus Master Control (BUM): Controls the bus master operation.
Bit 2: BUM
0
1
Description
Disable bus master operation
Enable bus master operation
(Initial value)
Bit 1—Memory Space Control (MES): Controls the access to the memory space when the PCIC
is operating as a target. When this bit is 0, all memory transfers to the PCIC are terminated by
master abort.
Bit 1: MES
0
1
Description
Disable access to memory space
Enable access to memory space
(Initial value)
Rev. 3.0, 04/02, page 816 of 1064