HD6417751 Datasheet, PDF (293/1105 Pages) Renesas Technology Corp – SuperH RISC engine

10.6 Output Clock Control
The CKIO pin can be switched between clock output and a high-impedance state by means of the
CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is
pulled up.
10.7 Overview of Watchdog Timer
10.7.1 Block Diagram
Figure 10.2 shows a block diagram of the WDT.
Standby
release
Standby
control
Internal reset
request
Reset
control
Interrupt
request
Interrupt
control
WDT
Frequency divider
Clock selection
Overflow
Clock selector
Clock
WTCSR
WTCNT
Standby
mode
Frequency
divider 2 ×1
clock
Bus interface
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
Figure 10.2 Block Diagram of WDT
Rev. 3.0, 04/02, page 253 of 1064