HD6417751 Datasheet, PDF (929/1105 Pages) Renesas Technology Corp – SuperH RISC engine

local bus. Only the linear mode is supported for addressing for burst transfers, and the 2 least
significant bits of the PCI address are regarded as B'00.
If a memory read line command or memory read multiple command is received, they operate as
memory reads. Similarly, when a memory write invalidate command is received, it functions as a
memory write.
Data must be set in the following registers prior to performing target transfers using memory read
or memory write commands: PCI configuration register 5 (PCICNF5), PCI configuration register
6 (PCICNF6), PCI local space register 0 (PCILSR [0]), PCI local space register 1 (PCILSR [1]),
PCI local address register 0 (PCILAR [0]), and PCI local address register 1 (PCILAR [1]).
PCICONF5 ³¹
(PCICONF6)
20 19
0
31
PCI address
0
PCIC access adjudication
31 28
20 19
0
PCILSR0
(PCILSR1)
000001111
31 28
20 19
0
PCILAR0
(PCILAR1)
31 28
0
Local address
Figure 22.4 Local Address Space Accessing Method
The PCIC supports two local address spaces (address space 0 and address space 1).
A certain range of the address space on the PCI bus corresponds to the local address space.
The local address space 0 is controlled by the PCICONF5, PCILAR0 and PCISR0. Figure 22.4
shows the method of accessing the local address space.
The PCICONF5 indicates the starting address of the memory space used by the PCI device. The
PCILAR0 specifies the starting address of the local address space 0. The PCILSR0 expresses the
size of the memory used by the PCI device. Regarding the method of setting each register, refer to
section 22.2, PCIC Register Descriptions.
Rev. 3.0, 04/02, page 889 of 1064