HD6417751 Datasheet, PDF (506/1105 Pages) Renesas Technology Corp – SuperH RISC engine

14.1.2 Block Diagram (SH7751)
Figure 14.1 shows a block diagram of the DMAC.
On-chip
peripheral
module
TMU
SCI, SCIF
DACK0, DACK1
DRAK0, DRAK1
DMAC module
Count
control
SARn
Register
control
DARn
Activation
control
DMATCRn
CHCRn
Request
priority
control
DMAOR
Bus
interface
4
dreq0-3
SAR0, DAR0, DMATCR0,
CHCR0 only
DDT module
,
DTR command buffer
D[31:0] ^{External bus}
ID[1:0]
32B data
buffer
Bus state
controller
DMAOR: DMAC operation register
SARn:
DMAC source address
register
DARn:
DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
(n: 0 to 3)
DBREQ
DDTMODE
BAVL
DDTD
id[1:0]
48 bits
tdack
CH0 CH1 CH2 CH3
Request controller
Figure 14.1 Block Diagram of DMAC
Rev. 3.0, 04/02, page 466 of 1064