HD6417751 Datasheet, PDF (22/1105 Pages) Renesas Technology Corp – SuperH RISC engine

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Block Diagram of SH7751 Series Functions ................................................. 10
Pin Arrangement (256-Pin QFP)................................................................... 11
Pin Arrangement (256-Pin BGA).................................................................. 12
Data Formats................................................................................................ 35
CPU Register Configuration in Each Processor Mode ................................... 38
General Registers ......................................................................................... 40
Floating-Point Registers ............................................................................... 42
Data Formats In Memory ............................................................................. 47
Processor State Transitions........................................................................... 49
Role of the MMU......................................................................................... 53
MMU-Related Registers............................................................................... 55
Physical Address Space (MMUCR.AT = 0) .................................................. 59
P4 Area........................................................................................................ 60
External Memory Space ............................................................................... 61
Virtual Address Space (MMUCR.AT = 1) .................................................... 62
UTLB Configuration .................................................................................... 65
Relationship between Page Size and Address Format .................................... 66
ITLB Configuration ..................................................................................... 69
Flowchart of Memory Access Using UTLB .................................................. 70
Flowchart of Memory Access Using ITLB.................................................... 71
Operation of LDTLB Instruction .................................................................. 73
Memory-Mapped ITLB Address Array......................................................... 81
Memory-Mapped ITLB Data Array 1 ........................................................... 82
Memory-Mapped ITLB Data Array 2 ........................................................... 83
Memory-Mapped UTLB Address Array ....................................................... 84
Memory-Mapped UTLB Data Array 1.......................................................... 85
Memory-Mapped UTLB Data Array 2.......................................................... 86
Cache and Store Queue Control Registers (CCR).......................................... 89
Configuration of Operand Cache (SH7751) .................................................. 92
Configuration of Operand Cache (SH7751R)................................................ 93
Configuration of Write-Back Buffer ............................................................. 97
Configuration of Write-Through Buffer ........................................................ 97
Configuration of Instruction Cache (SH7751) ............................................... 100
Configuration of Instruction Cache (SH7751R)............................................. 101
Memory-Mapped IC Address Array.............................................................. 104
Memory-Mapped IC Data Array................................................................... 105
Memory-Mapped OC Address Array ............................................................ 106
Memory-Mapped OC Data Array ................................................................. 107
Memory-Mapped IC Address Array.............................................................. 109
Memory-Mapped IC Data Array................................................................... 110
Memory-Mapped OC Address Array ............................................................ 111
Memory-Mapped OC Data Array ................................................................. 112
Rev. 3.0, 04/02, page xx of xxxviii