HD6417751 Datasheet, PDF (263/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 1—Clock Stop 1 (CSTP1): Specifies stopping of the peripheral clock supply to timer unit
(TMU) channels 3 and 4.
Bit 1: CSTP1
0
1
Description
Peripheral clock is supplied to TMU channels 3 and 4
(Initial value)
Peripheral clock supply to TMU channels 3 and 4 is stopped
Bit 0—Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt
controller (INTC). When this bit is set, PCIC and TMU channel 3 and 4 interrupts are not
detected.
Bit 0: CSTP0
0
1
Description
INTC detects PCIC and TMU channel 3 and 4 interrupts
(Initial value)
INTC does not detect PCIC and TMU channel 3 and 4 interrupts
9.2.6 Clock Stop Clear Register 00 (CLKSTPCLR00)
Clock stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that is used to clear
corresponding bits in the CLKSTP00 register.
Bit: 31
30
29
...
11
10
9
8
...
Initial value: 0
0
0
...
0
0
0
0
R/W: W
W
W
...
W
W
W
W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: W
W
W
W
W
W
W
W
Bits 31 to 0—Clock Stop Clear: The value of a Clock Stop Clear bit indicates whether the
corresponding Clock Stop bit is to be cleared. See section 9.2.5, Clock Stop Register 00
(CLKSTP00), for the correspondence between bits and the clocks stopped.
Bits 31 to 0
0
1
Description
Corresponding Clock Stop bit is not changed
Corresponding Clock Stop bit is cleared
(Initial value)
Rev. 3.0, 04/02, page 223 of 1064