HD6417751 Datasheet, PDF (429/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Refresh: The bus state controller includes a function for controlling DRAM refreshing.
Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing
the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported.
• CAS-before-RAS Refresh
When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals
determined by the input clock selected by bits CKS2–CKS0 in RTCSR, and the value set in
RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set so as to satisfy the
specification for the DRAM refresh interval. First make the settings for RTCOR, RTCNT, and
the RMODE and RFSH bits in MCR, then make the CKS2–CKS0 setting. When the clock is
selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT
value is constantly compared with the RTCOR value, and if the two values are the same, a
refresh request is generated and the %$&. pin goes high. If the SH7751 Series external bus
can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to
zero and the count-up is restarted. Figure 13.20 shows the operation of CAS-before-RAS
refreshing.
RTCNT value
RTCOR-1
RTCNT cleared to 0 when
RTCNT = RTCOR
H'00000000
Time
RTCSR.CKS2–0
= 000 ≠ 000
Refresh
request
External bus
Refresh request cleared
by start of refresh cycle
CAS-before-RAS refresh cycle
Figure 13.20 CAS-Before-RAS Refresh Operation
Figure 13.21 shows the timing of the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2–TRAS0 in
MCR. The specification of the RAS precharge time in the refresh cycle is determined by the
setting of bits TRC2–TRC0 in MCR.
Rev. 3.0, 04/02, page 389 of 1064