HD6417751 Datasheet, PDF (367/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify
the bus width of area n (n = 1 to 6).
(Bit 0): PORTEN Bit 2n + 1: AnSZ1
0
0
1
1
0
1
Bit 2n: AnSZ0
0
1
0
1
0
1
0
1
Description
Reserved (Setting prohibited)
Bus width is 8 bits
Bus width is 16 bits
Bus width is 32 bits
(Initial value)
Reserved (Setting prohibited)
Bus width is 8 bits
Bus width is 16 bits
Bus width is 32 bits
Bit 1—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 0—Port Function Enable (PORTEN): Specifies whether pins AD31 to AD0 are used as a
32-bit port. However, select PCI-disable mode when using this function.
Bit 0: PORTEN
0
1
Description
AD31 to AD0 are not used as a port
AD31 to AD0 are used as a port
(Initial value)
13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only)
Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of
either the MPX interface or the SRAM interface and specifies the burst length when the
synchronous DRAM interface is used.
BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. No external memory space other than area 0 should be accessed before register
initialization has been completed.
Rev. 3.0, 04/02, page 327 of 1064