HD6417751 Datasheet, PDF (529/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
DMAC Transfer DMAC Transfer Transfer Transfer
RS3 RS2 RS1 RS0 Request Source Request Signal Source Destination Bus Mode
1 0 0 0 SCI transmitter SCTDR1 (SCI External* SCTDR1 Cycle steal
transmit-data-
mode
empty transfer
request)
1 SCI receiver
SCRDR1 (SCI SCRDR1 External*
receive-data-full
transfer request)
Cycle steal
mode
1 0 SCIF transmitter SCFTDR2 (SCIF External* SCFTDR2 Cycle steal
transmit-data-
mode
empty transfer
request)
1 SCIF receiver SCFRDR2 (SCIF SCFRDR2 External* Cycle steal
receive-data-full
mode
transfer request)
1 0 0 TMU channel 2 Input capture
occurrence
External* External*
Burst/cycle
steal mode
1 TMU channel 2 Input capture
occurrence
External* On-chip Burst/cycle
peripheral steal mode
1 0 TMU channel 2 Input capture
occurrence
On-chip External*
peripheral
Burst/cycle
steal mode
TMU: Timer unit
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
Notes: * External memory or memory-mapped external device
1. SCI/SCIF burst transfer setting is prohibited.
2. If input capture interrupt acceptance is set for multiple channels and DE =1 for each
channel, processing will be executed on the highest-priority channel in response to a
single input capture interrupt.
3. A DMA transfer request by means of an input capture interrupt can be canceled by
setting TCR2.ICPE1 = 0 and TCR2.ICPE0 = 0 in the TMU.
To output a transfer request from an on-chip peripheral module, set the DMA transfer request
enable bit for that module and output a transfer request signal.
For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and
16, Serial Communication Interface with FIFO (SCIF).
When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral
module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs
every transfer in cycle steal mode, and in the last transfer in burst mode.
Rev. 3.0, 04/02, page 489 of 1064