HD6417751 Datasheet, PDF (508/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 14.2 DMAC Pins in DDT Mode
Pin Name
Data bus request
Data bus available
Abbreviation
'%5(4
('5(4)
%$9/
(DRAK0)
Transfer request signal 75
('5(4)
DMAC strobe
Channel number
notification
7'$&.
(DACK0)
ID [1:0]
(DRAK1, DACK1)
I/O
Input
Output
Input
Output
Output
Function
Data bus release request from external
device for DTR format input
Data bus release notification
Data bus can be used 2 cycles after
%$9/ is asserted
If asserted 2 cycles after %$9/
assertion, DTR format is sent
Only 75 asserted: DMA request
'%5(4 and 75 asserted
simultaneously: Direct request to
channel 2
Reply strobe signal for external device
from DMAC
Notification of channel number to
external device at same time as 7'$&.
output
(ID [1] = DRAK1, ID [0] = DACK1)
14.1.4 Register Configuration (SH7751)
Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers
are allocated to each channel, and an additional control register is shared by all four channels.
Table 14.3 DMAC Registers
Chan-
nel Name
Abbre-
viation
Read/
Area 7
Write Initial Value P4 Address Address
Access
Size
0
DMA source
SAR0
R/W Undefined H'FFA00000 H'1FA00000 32
address register 0
DMA destination DAR0
address register 0
R/W Undefined H'FFA00004 H'1FA00004 32
DMA transfer
count register 0
DMATCR0 R/W Undefined H'FFA00008 H'1FA00008 32
DMA channel
CHCR0
control register 0
R/W* H'00000000 H'FFA0000C H'1FA0000C 32
Rev. 3.0, 04/02, page 468 of 1064