HD6417751 Datasheet, PDF (714/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 16.12 shows an example of the operation for reception.
Start
1 _bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
Serial
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
0/1
data
RDF
FER
One frame
RXI interrupt
request
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 16.12 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
5. When modem control is enabled, the #%$ signal is output when SCFRDR2 is empty. When
#%$ is 0, reception is possible. When #%$ is 1, this indicates that SCFRDR2 contains a
number of data bytes equal to or greater than the #%$ output active trigger set number. The
#%$ output active trigger value is specified by bits 10 to 8 in the FIFO control register
(SCFCR2), described in section 16.2.9. RTS2 also goes to 1 when bit 4 (RE) in SCSCR2 is 0.
Figure 16.13 shows an example of the operation when modem control is used.
Serial data
RxD2
Start
bit
0 D0 D1 D2
Parity Stop
bit bit
D7 0/1 1
Start
bit
0
RTS2
Figure 16.13 Example of Operation Using Modem Control (RTS2)
Rev. 3.0, 04/02, page 674 of 1064