HD6417751 Datasheet, PDF (881/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 5—Mode 10 Pin Monitor (MD10): Monitors the 3&,5(4/MD10 pin value in a power-on
reset by means of the 5(6(7 pin.
Bit 5: MD10
0
1
Description
Host bridge function (arbitration) enabled
Host bridge function disabled
Bit 4—Mode 9 Pin Monitor (MD9): Monitors the 3&,5(4/MD9 pin value in a power-on reset
by means of the 5(6(7 pin.
Bit 4: MD9
0
1
Description
PCICLK used as PCI clock
Feedback input clock from CKIO used as PCI clock
Bit 3—$## Output (SERR): Software control of 6(55 output. This bit is valid only when bit
8 (SER) of the PCICONFI register is “1”. When “1” is written to this bit, 6(55 is asserted for 1
clock. This bit always returns “0” when read. Used when the PCIC is not the host. If used when
the PCIC is the host, an 6(55 assert interrupt is generated for the SH7751 Series.
Bit 3: SERR
0
1
Description
$## pin at Hi-Z
Assert $## (Low output)
(Initial value)
Bit 2— ,% Output (INTA): Software control of ,17$ (valid only when PCIC is not host)
Bit 2: INTA
0
1
Description
,17$ pin at Hi-Z (driven to High by pull-up resistor)
Assert ,17$ (Low output)
(Initial value)
Bit 1—PCIRST Output Control (RSTCTL): Controls the 3&,567 output. ORed with a power-
on reset before output. This field is reset only at a power-on reset. Do not use the field when the
PCIC is non-host.
Bit 1: PCIRST
0
1
Description
Negate 3&,567 (High output)
Assert 3&,567 (Low output)
(Initial value)
Rev. 3.0, 04/02, page 841 of 1064