HD6417751 Datasheet, PDF (589/1105 Pages) Renesas Technology Corp – SuperH RISC engine

11. Clearing DDT mode
Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT
bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode,
the DMAC will freeze.
This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT
mode.
12. Confirming DMA transfer requests and number of transfers executed
The channel associated with a DMA bus cycle being executed in response to a DMA transfer
request can be confirmed by determining the level of external pins ID1 and ID0 at the rising
edge of the CKIO clock while 7'$&. is asserted.
(ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3)
Rev. 3.0, 04/02, page 549 of 1064