HD6417751 Datasheet, PDF (1042/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Address
RD/
D31–D0
(read)
D31–D0
(write)
Tnop Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
t_AD
c1
c2
t_CASD1
t_CASD1
t_AD
c8
t_CSD
t_RWD
RAS down
mode ended
t_RASD
t_CASD1
t_CASD1
t_WDD
t_RDS
t_RDH
d1
d2
t_WDD
d1
d2
t_BSD t_BSD
t_RDS
d8
t_RDH
d8
t_WDD
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
t_DACD
t_DACD
t_DACD
t_DACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)
Rev. 3.0, 04/02, page 1002 of 1064