HD6417751 Datasheet, PDF (747/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Section 18 I/O Ports
18.1 Overview
The SH7751 Series has a 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port.
18.1.1 Features
The features of the general-purpose I/O port are as follows:
• Available only in PCI-disabled mode.
• 32-bit I/O port with input/output direction independently specifiable for each bit.
• Pull-up can be specified independently for each bit.
• The 32 bits of the general-purpose I/O port are divided into 16-bit port A and 16-bit port B.
Interrupts can be input to 16-bit port A.
• Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2
(BCR2). (Do not set PORTEN = 1 when in PCI-enabled mode.)
The features of the SCI I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCI enabling has not been
set. This allows break function transmission.
• The RxD pin value can be read at all times, allowing break state detection.
• SCK pin control is possible when the I/O port is designated for output and SCI enabling has
not been set.
• The SCK pin value can be read at all times.
The features of the SCIF I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCIF enabling has not been
set. This allows break function transmission.
• The RxD2 pin value can be read at all times, allowing break state detection.
• SCK2, %$, and #%$ pin control is possible when the I/O port is designated for output and
SCIF enabling has not been set.
• The SCK2, %$, and #%$ pin values can be read at all times.
Rev. 3.0, 04/02, page 707 of 1064