HD6417751 Datasheet, PDF (27/1105 Pages) Renesas Technology Corp – SuperH RISC engine

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Dual Address Mode/Burst Mode External Bus → External Bus/
'5(4 (Edge Detection), DACK (Read Cycle) ............................................. 508
Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) →
External Bus................................................................................................. 509
Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI
(Level Detection) ......................................................................................... 510
Single Address Mode/Cycle Steal Mode External Bus → External Bus/'5(4
(Level Detection) ......................................................................................... 511
Single Address Mode/Cycle Steal Mode External Bus → External Bus/'5(4
(Edge Detection) .......................................................................................... 512
Single Address Mode/Burst Mode External Bus → External Bus/'5(4
(Level Detection) ......................................................................................... 513
Single Address Mode/Burst Mode External Bus → External Bus/'5(4
(Edge Detection) .......................................................................................... 514
Single Address Mode/Burst Mode External Bus → External Bus/'5(4
(Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM:
Row Hit Write) ............................................................................................ 515
On-Demand Transfer Mode Block Diagram.................................................. 520
System Configuration in On-Demand Data Transfer Mode............................ 522
Data Transfer Request Format ...................................................................... 523
Single Address Mode/Synchronous DRAM → External Device Longword
Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS
latency=3, TPC=3) ....................................................................................... 526
Single Address Mode/External Device → Synchronous DRAM Longword
Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1,
TRWL=2, TPC=1) ....................................................................................... 527
Dual Address Mode/Synchronous DRAM →SRAM Longword Transfer....... 528
Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 529
Single Address Mode/Burst Mode/External Device → External Bus 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 529
Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ............................................. 530
Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ............................................. 531
Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) 532
Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data
Transfer) ...................................................................................................... 533
Read from Synchronous DRAM Precharge Bank .......................................... 534
Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ............... 534
Read from Synchronous DRAM (Row Hit)................................................... 535
Write to Synchronous DRAM Precharge Bank.............................................. 535
Write to Synchronous DRAM Non-Precharge Bank (Row Miss)................... 536
Rev. 3.0, 04/02, page xxv of xxxviii