HD6417751 Datasheet, PDF (420/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.14. Tpc is the precharge cycle, Tr the 5$6 assert cycle, Tc1 the &$6 assert cycle, and
Tc2 the read data latch cycle.
CKIO
Address
Tr1
Tr2
Tc1
Tc2
Tpc
Row
Column
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Notes: IO : DACK device
SA : Single address DMA transfer
DA : Dual address DMA transfer
The DACK is in the high-active setting
For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.14 Basic DRAM Access Timing
Rev. 3.0, 04/02, page 380 of 1064