HD6417751 Datasheet, PDF (1102/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Appendix G Power-On and Power-Off Procedures
• Power-on
 Supply the internal power after supplying power to the I/O, RTC, and CPG.*
 Supply power to V_DDQ, V , _DD-RTC and V_DD-CPG simultaneously.
 At power-on, the #$% signal is low. Normally, supply power to the I/O, RTC, and CPG
before (or at the same time as) entering the signal lines (#$%, #$%, MD0 to
MD10, and external clock). If the signal lines are entered first, the LSI may be damaged.
 Input high level to #$% in compliance with the voltage level of the I/O, RTC, CPG
power supply voltage.
• Power-off
 When turning off the power, there are no restrictions for the timing of #$%, #$%.
 Turn off the I/O, RTC, CPG power supply voltage after (or at the same time as)* turning
off the internal power supply voltage.
Note however that the internal power supply voltage may exceed the I/O, RTC, CPG power
supply voltage by a maximum of 0.3 V only when the system is being turned off.
 The power supply level must be lowered in compliance with the I/O, RTC, CPG power
supply voltage.
Note: * 10 ms or less for the HD6417751R.
• The ratings and procedures for power-on and power-off are given below.
V_DDQ = V_DD-RTC = V_DD-CPG = 0 V
The LSI may be damaged if
−0.3 V < V_in < V_DDQ + 0.3 V
−0.3 V < V_DD, V_DD-PLL1/2 < V_DDQ + 0.3 V
are not satisfied when V_DDQ = V_DD-RTC = V . _DD-CPG
2.0 V
Power-on
1.2 V
GND
t_on
0 ≤ t_on < 10 ms*
Note: * HD6417751R only
V_DDQ
V_DD, V_DD-PLL1/2
Power-off
t_off
0 ≤ t_off < 10 ms*
Figure G.1 Power-On and Power-Off Procedures
Rev. 3.0, 04/02, page 1062 of 1064