HD6417751 Datasheet, PDF (37/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Table 15.9
Table 15.10
Table 15.11
Table 15.12
Table 15.13
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Table 17.7
Table 17.8
Table 17.9
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 19.1
Table 19.2
Table 19.3
Table 19.4
Table 19.5
Table 19.6
Table 19.7
Table 19.8
Table 20.1
Table 21.1
Table 21.2
SCI Registers.................................................................................................. 572
Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ............. 591
Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode ............... 594
Maximum Bit Rate for Various Frequencies with Baud Rate Generator
(Asynchronous Mode) .................................................................................... 595
Maximum Bit Rate with External Clock Input (Asynchronous Mode).............. 596
Maximum Bit Rate with External Clock Input (Synchronous Mode)................ 596
SCSMR1 Settings for Serial Transfer Format Selection................................... 598
SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection ..................... 598
Serial Transfer Formats (Asynchronous Mode) ............................................... 600
Receive Error Conditions................................................................................ 608
SCI Interrupt Sources ..................................................................................... 627
SCSSR1 Status Flags and Transfer of Receive Data ........................................ 628
SCIF Pins ....................................................................................................... 636
SCIF Registers ............................................................................................... 636
SCSMR2 Settings for Serial Transfer Format Selection................................... 663
SCSCR2 Settings for SCIF Clock Source Selection......................................... 664
Serial Transfer Formats................................................................................... 665
SCIF Interrupt Sources ................................................................................... 675
Smart Card Interface Pins ............................................................................... 681
Smart Card Interface Registers........................................................................ 681
Smart Card Interface Register Settings ............................................................ 689
Values of n and Corresponding CKS1 and CKS0 Settings ............................... 691
Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) ... 692
Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ................ 692
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ........ 692
Register Settings and SCK Pin State ............................................................... 693
Smart Card Mode Operating States and Interrupt Sources................................ 700
32-Bit General-Purpose I/O Port Pins.............................................................. 715
SCI I/O Port Pins............................................................................................ 717
SCIF I/O Port Pins.......................................................................................... 717
I/O Port Registers ........................................................................................... 718
INTC Pins ...................................................................................................... 731
INTC Registers............................................................................................... 731
– ,5/ ,5/ Pins and Interrupt Levels ............................................................. 734
Interrupt Exception Handling Sources and Priority Order ................................ 737
Interrupt Request Sources and IPRA–IPRD Registers...................................... 740
Interrupt Request Sources and INTPRI00 Register .......................................... 743
Bit Allocation................................................................................................. 746
Interrupt Response Time................................................................................. 750
UBC Registers................................................................................................ 753
H-UDI Pins .................................................................................................... 779
H-UDI Registers............................................................................................. 780
Rev. 3.0, 04/02, page xxxv of xxxviii