HD6417751 Datasheet, PDF (477/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
/
D31–D0
Tm1
Tmd1
A
D0
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait)
Rev. 3.0, 04/02, page 437 of 1064