HD6417751 Datasheet, PDF (783/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 19.6 Interrupt Request Sources and INTPRI00 Register
Bits
Register
31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4 3 to 0
Interrupt priority
level setting
register
Reserved Reserved Reserved Reserved TMU ch4 TMU ch3 PCI (1) PCI (0)
Note: Reserved bits: These bits always read as 0, and should only be written with 0.
As shown in table 19.6, 8 combinations of internal peripheral modules are assigned to one register.
Values of H'F (1111) to H'0 (0000) can be set in each 4 bits, allowing the order levels of the
corresponding interrupts to be set. H'F is priority level 15 (highest level) while H'0 is priority level
0 (request mask).
Reserved: These bits are always read as 0, and should only be written with 0.
19.3.4 Interrupt Factor Register 00 (INTREQ00)
The interrupt factor register 00 (INTREQ00) shows which interrupt have been requested of the
INTC. Even when the interrupts are masked with INTPRI00 and INTMSK00, the bits in this
register are not affected. INTREQ00 is a 32-bit read-only register.
Bit: 31
30
29
...
11
10
9
8
...
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 31 to 0—Interrupt Request: These bits indicate the existence of an interrupt request
corresponding to each bit. For the correspondence between bits and interrupt sources, see section
19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation.
Bits 31 to 0
0
1
Description
Shows no corresponding interrupt request
Shows existence of corresponding interrupt request
(Initial value)
Rev. 3.0, 04/02, page 743 of 1064