HD6417751 Datasheet, PDF (845/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 22.1 Pin Configuration (cont)
PCI
No. Pin Name ^Standard
Signal
Name
Function
I/O Pull-up
Type Resistor*¹
I/O Status
in Operating Modes
Host
Non-host
Remarks
Master Target Master Target
18 3&,5(4/ 5(4 Bus request (host t/s
Yes
I
I
—
—
MD10
function)
Host bridge
in
function ON/OFF
I
I
I
I
*²
19 3&,5(4 5(4 Bus request
t/s
Yes
I
I
—
—
(host function)
20 3&,*17 *17 to Bus grant
t/s
to
*17 (host function)
3&,*17
O
O
—
—
21 IDSEL
IDSEL Config device
in
select
—
—
I
I
*³
in: Input
out: Output
s/t/s: Sustained try state
o/d: Open drain
t/s: Try state
Notes: *1 Terminal provided with a pull-up resistor.
*2 The values of external pins are sampled in a power-on reset by means of the #$% pin.
*3 This must be fixed at Low when not in used.
22.1.4 Register Configuration
The PCIC has the PCI configuration registers and PCI control registers shown in table 22.2, 22.3
and 22.4. Also, the PCI bus address space is allocated to the internal bus for the peripheral
modules, making it possible to access the PCI bus by program IO (PIO). Not only do these
registers control the PCI bus but also enable high-speed data transfers between the PCI device and
memory on the SH-4 external data bus (hereinafter, the SH-4 external data bus is referred to as the
local bus to distinguish it from the PCI bus).
Rev. 3.0, 04/02, page 805 of 1064