HD6417751 Datasheet, PDF(889/1105 Page) Renesas Technology Corp – SuperH RISC engine

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HD6417751 Datasheet, PDF (889/1105 Pages) Renesas Technology Corp – SuperH RISC engine

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from both the PP bus and PCI bus. When set to 0, the respective interrupt is disabled, and enabled

when set to 1.

The PCIINTM register is initialized to H'00000000 at a power-on reset and software reset.

Bits 31 to 16âReserved: These bits always return 0 when read. Always write 0 to these bits.

Bit 15âUnlocked Transfer Detection Interrupt Mask (M_LOCKON)

Bit 14âTarget Target Abort Interrupt Mask (T_TGT_ABORT)

Bits 13 to 10âReserved: These bits always return 0 when read. Always write 0 to these bits.

Bit 9âTarget Retry Timeout Interrupt Mask (TGT_RETRY)

Bit 8âMaster Function Disable Error Interrupt Mask (MST_DIS)

Bit 7âAddress Parity Error Detection Interrupt Mask (ADRPERR)

Bit 6â$## Detection Interrupt Mask (SERR_DET)

Bit 5âTarget Write Data Parity Error Interrupt Mask (T_DPERR_WT)

Bit 4âTarget Read !## Detection Interrupt Mask (T_PERR_DET)

Bit 3âMaster Target Abort Interrupt Mask (M_TGT_ABORT)

Bit 2âMaster Master Abort Interrupt Mask (M_MST_ABORT)

Bit 1âMaster Write Data Parity Error Interrupt Mask (M_DPERR_WT)

Bit 0âMaster Read Data Parity Error Interrupt Mask (M_DPERR_RD)

Rev. 3.0, 04/02, page 849 of 1064

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