HD6417751 Datasheet, PDF (860/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 31—BIST7: BIST function support
Bit 31: BIST7
0
1
Description
Function not supported
Function supported (not supported)
(Initial value)
Bit 30—BIST6: Used to control the BIST starting.
Bit 30: BIST6
0
1
Description
Execution completed
Executing (not supported)
(Initial value)
Bits 29 and 28—BIST5 and 4: These bits always return 0 when read.
Bits 27 to 24—BIST3 to 0: BIST status on completion of operation.
Bits 27 to 24:
BIST3 to 0
H'0
H'1 to H'F
Description
Passed test
Test failed (not supported)
(Initial value)
Bit 23—Multifunction Status (HEAD7): Shows whether the device is a multi-function unit or a
single-function unit.
Bit 23: HEAD7
0
1
Description
Single-function device
Device has between 2 and 8 functions (not supported)
(Initial value)
Bits 22 to 16—Configuration Layout Type (HEAD6 to 0): These bits indicate the layout type of
the configuration register.
Bits 22 to 16:
HEAD6 to 0
H'00
H'01
H'02 to H'3F
Description
Type 00h layout supported
Type 01h layout supported (not supported)
Reserved
(Initial value)
Bits 15 to 8—Latency Timer Register (LAT7 to 0): These bits specify the latency time of the
PCI bus when the PCIC is operating as the master.
Rev. 3.0, 04/02, page 820 of 1064