HD6417751 Datasheet, PDF (882/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 0—PCIC Internal Register Initialization Control Bit (CFINIT): After the SH initializes
the PCI registers, setting this bit enables access from the PCI bus. During initialization, no bus
privileges are granted to other devices on the PCI bus while operating as the host. When operating
not as the host, a retry is returned without the access from the PCI bus being accepted.
Bit 0: CFINIT
0
1
Description
Initialization busy
Initialization complete
(Initial value)
22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0])
Bit: 31
30
29
28
27
26
25
24
—
—
— PLSR28 PLSR27 PLSR26 PLSR25 PLSR24
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
PLSR23 PLSR22 PLSR21 PLSR20 —
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
The PCI local space register [1:0] (PCILSR [1:0]) specifies the capacities of the two local address
spaces (address space 0 and address space 1) supported when a device on the PCI bus performs a
Rev. 3.0, 04/02, page 842 of 1064