HD6417751 Datasheet, PDF (817/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Section 21 Hitachi User Debug Interface (H-UDI)
21.1 Overview
21.1.1 Features
The Hitachi user debug interface (H-UDI) is a serial input/output interface conforming to JTAG,
IEEE 1149.1, and IEEE Standard Test Access Port and Boundary-Scan Architecture. The SH7751
Series H-UDI support boundary-scan, and is used for emulator connection. The functions of this
interface should not be used when using an emulator. Refer to the emulator manual for the method
of connecting the emulator. The H-UDI uses six pins (TCK, TMS, TDI, TDO, 7567, and
$6(%5./BRKACK). In the SH7751 Series, six dedicated emulator pins have been added
(AUDSYNC, AUDCK, and AUDATA3 to AUDATA0). The pin functions and serial transfer
protocol conform to the JTAG specifications.
21.1.2 Block Diagram
Figure 21.1 shows a block diagram of the H-UDI. The TAP (test access port) controller and
control registers are reset independently of the chip reset pin by driving the 7567 pin low or
setting TMS to 1 and applying TCK for at least five clock cycles. The other circuits are reset and
initialized in an ordinary reset. The H-UDI circuit has six internal registers: SDBPR, SDBSR,
SDIR, SDINT, SDDRH, and SDDRL (these last two together designated SDDR). The SDBPR
register supports the JTAG bypass mode, SDBSR is a shift register forming a JTAG boundary
scan, SDIR is the command register, SDDR is the data register, and SDINT is the H-UDI interrupt
register. SDIR can be accessed directly from the TDI and TDO pins.
Rev. 3.0, 04/02, page 777 of 1064