HD6417751 Datasheet, PDF (307/1105 Pages) Renesas Technology Corp – SuperH RISC engine

11.2 Register Descriptions
11.2.1 64 Hz Counter (R64CNT)
R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC
frequency divider.
If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7
(CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the
carry and the 64 Hz counter read. In this case, the read value is not valid, and so R64CNT must be
read again after first writing 0 to the CF bit in RCR1 to clear it.
When the RESET bit or ADJ bit in RTC control register 2 (RCR2) is set to 1, the RTC frequency
divider is initialized and R64CNT is initialized to H'00.
R64CNT is not initialized by a power-on or manual reset, or in standby mode.
Bit 7 is always read as 0 and cannot be modified.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
—
1 Hz
2 Hz
4 Hz
8 Hz 16 Hz 32 Hz 64 Hz
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
R
R
R
R
R
R
R
11.2.2 Second Counter (RSECCNT)
RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the
BCD-coded second value in the RTC. It counts on the carry (transition of the R69CNT.1Hz bit
from 0 to 1) generated once per second by the 64 Hz counter.
The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set.
Write processing should be performed after stopping the count with the START bit in RCR2, or
by using the carry flag.
RSECCNT is not initialized by a power-on or manual reset, or in standby mode.
Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
—
10-second units
1-second units
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 267 of 1064