HD6417751 Datasheet, PDF (936/1105 Pages) Renesas Technology Corp – SuperH RISC engine

DMA Arbitration: If transfer requests are made simultaneously on multiple DMA channels in the
PCI, transfer arbitration is required. There are two modes that can be selected to determine order
of priority of the DMA transfers on the four channels: fixed order of priority and pseudo round-
robin. The mode is selected using the DMABT bit of the PCI's DMA transfer arbitration register
(PCIDMABT).
For arbitration to be performed in such a way as to maintain high-speed data transfer, there are 4
FIFOs (32-byte × 2 buffer structure) for the four DMA transfer channels. The FIFOs have a 2-
buffer structure, enabling one buffer to be accessed from the PCI bus while the other is being
accessed from the local bus. Depending on the direction of the transfer, the input port of the FIFO
for DMA transfers. Transfers are possible in both directions between the local bus and PCI bus by
selecting the transfer direction.
The arbitration circuit monitors the data transfer requests (data write requests to the FIFO when
the FIFO is empty and read requests from the FIFO when it is full) 4 DMA transfer channels to
control the data transfers.
If a DMA transfer request occurs at the same time as a PIO transfer request, the PIO transfer takes
precedence over transfers on the four DMA channels, regardless of the specified mode of DMA
transfer priority order.
Fixed Priority Mode (DMABT = 0): In fixed priority mode, the order of priority of data transfer
requests is fixed and cannot be changed. The order is as follows:
Channel 0 DMA transfer > channel 1 DMA transfer > channel 2 DMA transfer >
channel 3 DMA transfer
DMA transfer on channel 0. Take the highest priority and channel 3 DMA transfers take the
lowest priority. When data transfer requests occur simultaneously, the data transfer with the
highest priority takes precedence.
Let's look at data transfers from the local bus to the PCI bus in fixed priority mode. The arbitration
circuit monitors the transfer requests from the respective data transfer control circuits and writes
data read from the local bus to the data transfer FIFO that not only is empty but also has the
highest priority.
On the other hand, it checks if transfer data exists in the respective FIFOs and reads that data from
the data transfer FIFO in which there is data and which has the highest priority, and outputs that
data to the PCI bus.
For example, if channel 1 FIFO is empty, the arbitration circuit writes the data from the local bus
into the channel 1 FIFO. Next, if data of 32bytes or more is in the channel 1 FIFO, it outputs that
data to the PCI bus.
Rev. 3.0, 04/02, page 896 of 1064