HD6417751 Datasheet, PDF (384/1105 Pages) Renesas Technology Corp – SuperH RISC engine

13.2.8 Memory Control Register (MCR)
The memory control register (MCR) is a 32-bit readable/writable register that specifies 5$6 and
&$6 timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address
multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected
without using external circuitry.
MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE,
SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a power-
on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Bit: 31
30
29
28
27
26
25
24
RASD MRSET TRC2 TRC1 TRC0
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R
R
R
Bit: 23
22
21
20
19
18
17
16
TCAS
—
TPC2 TPC1 TPC0
—
RCD1 RCD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W
R/W
R/W
R
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 BE
SZ1
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
6
5
SZ0 AMXEXT AMX2
0
0
0
R/W
R/W
R/W
4
AMX1
0
R/W
3
AMX0
0
R/W
2
RFSH
0
R/W
1
RMODE
0
R/W
0
EDO
MODE
0
R/W
Rev. 3.0, 04/02, page 344 of 1064