HD6417751 Datasheet, PDF (1012/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A5
A4–A0
RD/
D31–D0
(read)
T1 TB2 TB1 TB2 TB1 TB2 TB1 T2
t_AD
t_AD
t_AD
t_CSD
t_RWD
t_{RSD tRSD}
t_RDS
t_RDH
t_BSD t_BSD
t_CSD
t_RWD
t_RSD
t_RDS
t_RDH
DACKn
(SA: IO ← memory)
DACKn
(DA)
t_DACD t_{DACD tDACD}
t_DACD
t_DACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.17 Burst ROM Bus Cycle (No Wait)
Rev. 3.0, 04/02, page 972 of 1064