HD6417751 Datasheet, PDF (865/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 0—LA0ASI: Shows whether the base address specified by this register is an I/O space or
memory space.
Bit 0: LA0ASI
0
1
Description
Memory space
I/O space
(Initial value)
22.2.7 PCI Configuration Register 6 (PCICONF6)
Bit: 31
30
29
28
27
26
25
24
BASE131 BASE130 BASE129 BASE128 BASE127 BASE126 BASE125 BASE124
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
BASE123 BASE122 BASE121 BASE120 BASE119 BASE118 BASE117 BASE116
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R/W
R/W
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
BASE115 BASE114 BASE113 BASE112 BASE111 BASE110 BASE19 BASE18
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
BASE17 BASE16 BASE15 BASE14 LA1PREF LA1TYPE1 LA1TYPE0 LA1ASI
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
The PCI configuration register 6 (PCICONF6) is a 32-bit read/partial-write register that
accommodates the memory space base address PCI configuration register stipulated in the PCI
local bus specifications. This register contains the most significant bits (maximum 12 in bits 31 to
20) of the address used when a device on the PCI bus accesses local memory on the SH local bus
Rev. 3.0, 04/02, page 825 of 1064