HD6417751 Datasheet, PDF (910/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.35 PCI Power Management Interrupt Register (PCIPINT)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
PCI-R/W: —
—
—
...
—
—
—
—
PP Bus-R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
—
—
—
—
—
Initial value: 0
0
0
0
0
PCI-R/W: —
—
—
—
—
PP Bus-R/W: R
R
R
R
R
Note: Cleared by setting WC:1. (Writing of 0 is ignored.)
2
1
0
— PWRST_ PWRST_
D3
D0
0
0
0
—
—
—
R
R/WC R/WC
The PCI power management interrupt register (PCIPINT) controls the power management
interrupts. It provides the interrupt bits for a transition to the power state D3 (power down mode)
and recovery to the power state D0 (normal state). This 32-bit read/write register can be accessed
from the PP bus.
The PCIPINT register is initialized to H'00000000 at a power-on reset. It is not initialized at a
software reset. When an interrupt is detected, the bit corresponding to the content of that interrupt
is set to 1. Each interrupt detection bit can be cleared to 0 by writing 1 to it (write clear).
The power state D0 interrupt is not generated at a power-on reset.
Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 1—Power state D3 (PWRST_D3): Transition request to power-down mode interrupt for
SH7751 and SH7751R.
Bit 0—Power state D0 (PWRST_D0): Restore from power-down mode interrupt for SH7751
and SH7751R.
Note: The power states D3, D0 are not masked even when the interrupt mask bit is set ON.
Rev. 3.0, 04/02, page 870 of 1064