HD6417751 Datasheet, PDF (1056/1105 Pages) Renesas Technology Corp – SuperH RISC engine

HD6417751 HD6417751 HD6417751 HD6417751
RBP240 RBP200 RF240
RF200
*²
*²
*²
*²
Module Item
Symbol Min Max Min Max Min Max Min Max Unit Figure Notes
DMAC '5(4Q
t_DRQS
setup time
2—
2.5 —
3.5 —
3.5 — ns
23.64
'5(4Q
t_DRQH
hold time
1.5 —
1.5 —
1.5 —
1.5 — ns 23.64
DRAKn
delay time
t_DRAKD
1.5 5.3
1.5 5.3
1.5 6
1.5 6 ns 23.64
INTC
NMI pulse t_NMIH
width (high)
5—
5—
5—
5
—
t_cyc
23.69 Normal
or sleep
mode
30 —
30 —
30 —
30 — ns
23.69 Standby
mode
NMI pulse t_NMIL
width (low)
5—
5—
5—
5
—
t_cyc
23.69 Normal
or sleep
mode
30 —
30 —
30 —
30 — ns
23.69 Standby
mode
H-UDI Input clock t_TCKcyc
cycle
50 —
50 —
50 —
50 — ns
23.65,
23.67
Input clock t_TCKH
pulse width
(high)
15 —
15 —
15 —
15 — ns 23.65
Input clock t_TCKL
pulse width
(low)
15 —
15 — 15 — 15 — ns 23.65
Input clock t_TCKr
rise time
— 10 — 10 — 10 — 10 ns 23.65
Input clock t_TCKf
fall time
— 10 — 10 — 10 — 10 ns 23.65
$6(%5.
t_ASEBRKS
10
—
setup time
10 —
10 —
10 — t_cyc
23.66
$6(%5.
hold time
t_ASEBRKH
10
—
10 —
10 —
10 — t_cyc
23.66
TDI/TMS
t_TDIS
setup time
15 — 15 — 15 — 15 — ns 23.67
TDI/TMS
t_TDIH
hold time
15 — 15 — 15 — 15 — ns 23.67
TDO delay t_TDO
time
0 10
ASE-
PINBRK
t_PINBRK
2
—
pulse width
0 10
2—
0 10
2—
0 10 ns 23.67
2 — Pcyc*¹ 23.68
Notes: *1 Pcyc: P clock cycles
*2 V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, Ta = –20 to +75°C, C_L = 30 pF, PLL2 on
Rev. 3.0, 04/02, page 1016 of 1064