HD6417751 Datasheet, PDF (857/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 0—I/O Space Control (IOS): Controls the access to the I/O space when the PCIC is
operating as a target. When this bit is 0, all I/O transfers to the PCIC are terminated by master
abort.
Bit 0: IOS
0
1
Description
Disable access to I/O space
Enable access to I/O space
(Initial value)
22.2.3 PCI Configuration Register 2 (PCICONF2)
Bit: 31
30
29
28
27
26
25
24
CLASS23 CLASS22 CLASS21 CLASS20 CLASS19 CLASS18 CLASS17 CLASS16
Initial value: —
—
—
—
—
—
—
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
CLASS15 CLASS14 CLASS13 CLASS12 CLASS11 CLASS10 CLASS9 CLASS8
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
CLASS7 CLASS6 CLASS5 CLASS4 CLASS3 CLASS2 CLASS1 CLASS0
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
REVID7 REVID6 REVID5 REVID4 REVID3 REVID2 REVID1 REVID0
Initial value:
*
*
*
*
*
*
*
*
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
*: Initial values vary with the logic versions of the chip.
The PCI configuration register 2 (PCICONF2) is a 32-bit read/partial-write register that includes
the class code and revision ID PCI configuration registers stipulated in the PCI local bus
Rev. 3.0, 04/02, page 817 of 1064