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HD6417751 Datasheet, PDF (812/1105 Pages) Renesas Technology Corp – SuperH RISC engine
Exception/interrupt
generation
Hardware operation
SPC ← PC
SSR ← SR
SR.BL ← B'1
SR.MD ← B'1
SR.RB ← B'1
Exception
EXPEVT ← exception code
Exception/
interrupt/trap?
Interrupt
INTEVT ← interrupt code
Trap
EXPEVT ← H'160
TRA ← TRAPA (imm)
SGR ← R15
No
Yes
Reset exception?
Yes
(BRCR.UBDE == 1) &&
No
(user break exception)?
PC ← DBR
PC ← VBR + vector offset
PC ← H'A0000000
Debug program
R15 ← SGR
(STC instruction)
Exception handling routine
Execute RTE instruction
PC ← SPC
SR ← SSR
End of exception
operations
Figure 20.2 User Break Debug Support Function Flowchart
Rev. 3.0, 04/02, page 772 of 1064