HD6417751 Datasheet, PDF (862/1105 Pages) Renesas Technology Corp – SuperH RISC engine

In the SH7751, the 12 higher-order bits (bits 31 to 8) are set; in the SH7751R, the 24 higher-order
bits are set. As the I/O space for the PCI bus, allocate 1 Mbyte of space for the SH7751 and 256
bytes of space for the SH7751R.
In the SH7751, bits 30 to 20 are writable, and bits 19 to 2 and 0 are fixed by the hardware.
In the SH7751R, bits 31 to 8 are writable, and bits 7 to 2 and 0 are fixed by the hardware.
The PCICONF4 register is initialized to H'00000001 at a power-on reset and software reset.
Always write to this register prior to executing I/O transfers (accessing the local registers in the
PCIC) to or from the PCIC from the PCI bus.
Bits 31 to 8—Base Address of the I/O Space (BASE 31 to 8): Sets the base address of the local
registers (I/O space) in the PCIC. In the SH7751, bits 19 to 8 are fixed to H'000 in hardware.
Bits 7 to 2—Base Address of the I/O Space (BASE 7 to 2): Fixed at H'00 in hardware.
Bit 1—Reserved: This bit always returns 0 when read. Always write 0 to this bit.
Bit 0—Address Space Indicator (ASI): Shows whether the base address specified by this
register is an I/O space or memory space.
Bit 0: ASI
0
1
Description
Memory space
I/O space
(Initial value)
Rev. 3.0, 04/02, page 822 of 1064