HD6417751 Datasheet, PDF (897/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 3—REQ3 Error (REQ3ID): Error occurred when device 3 (REQ3) was bus master.
Bit 2—REQ2 Error (REQ2ID): Error occurred when device 2 (REQ2) was bus master.
Bit 1—REQ1 Error (REQ1ID): Error occurred when device 1 (REQ1) was bus master.
Bit 0—REQ0 Error (REQ0ID): Error occurred when device 0 (REQ0) was bus master.
22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
PCI-R/W: R
R
R
...
R
R
R
R
PP Bus-R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— DMABT
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R/W
PP Bus-R/W: R
R
R
R
R
R
R
R/W
The PCI DMA transfer arbitration register (PCIDMABT) is a register that controls the arbitration
mode in the case of DMA transfers. Two types of DMA arbitration mode can be selected: priority-
fixed and pseudo round-robin. This 32-bit read/write register can be accessed from both the PP
bus and PCI bus.
The PCIDMABT register is initialized to H'00000000 at a power-on reset or software reset.
Always write to this register to specify the DMA transfer arbitration mode prior to starting DMA
transfers.
Bits 31 to 1—Reserved: These bits always returns 0 when read. Always write 0 to these bits
when writing.
Bit 0—DMA3 Arbitration Mode (DMABT): Controls the DMA arbitration mode.
Bit 0: DMABT
0
1
Description
Priority-fixed (Channel 0 > Channel 1 > Channel 2 > Channel 3)
(Initial value)
Pseudo round-robin
Rev. 3.0, 04/02, page 857 of 1064