HD6417751 Datasheet, PDF (861/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 7 to 0—Cache Line Size (CACHE7 to 0): Not supported. Memory target is set cache-
disabled, and SDONE and 6%2 are ignored.
22.2.5 PCI Configuration Register 4 (PCICONF4)
Bit: 31
30
29
28
27
26
25
24
BASE31 BASE30 BASE29 BASE28 BASE27 BASE26 BASE25 BASE24
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R/W
R/W R/W* R/W* R/W* R/W*
PP Bus-R/W: R/W
R/W
R/W
R/W R/W* R/W* R/W* R/W*
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
15
14
13
12
11
10
BASE15 BASE14 BASE13 BASE12 BASE11 BASE10
0
0
0
0
0
0
R/W* R/W* R/W* R/W* R/W* R/W*
R/W* R/W* R/W* R/W* R/W* R/W*
9
BASE9
0
R/W*
R/W*
8
BASE8
0
R/W*
R/W*
Bit: 7
6
5
4
3
2
1
0
BASE7 BASE6 BASE5 BASE4 BASE3 BASE2 —
ASI
Initial value: 0
0
0
0
0
0
0
1
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Note: * These bits are read-only in the SH7751 and can be read from and written to in the
SH7751R.
PCI configuration register 4 (PCICONF4) is a 32-bit read/partial-write register that accommodates
the I/O-space base address register, which is one of the PCI configuration registers that are
stipulated in the PCI’s local-bus specifications. PCICONF4 holds the higher-order bits of the
address used when a device on the PCI bus uses I/O transfer commands to access a local register
in the PCIC.
Rev. 3.0, 04/02, page 821 of 1064